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Given the scale and mission-critical nature of production networks today, it is essential to solidify their resilience to link failures. Building this resilience in each application separately is not scalable. In order to minimize downtime, at least some degree of resilience should be built directly into the data plane. Fast Failover groups in OpenFlow offer a mechanism to achieve this, but programming them introduces additional complexity to the existing arduous task of developing an SDN controller application. In this paper, we discuss how this complexity can be decoupled from the controller implementation. We introduce FORTIFY, a transparent resiliency layer that incorporates data plane fault tolerance into any existing controller application without any modification to it. FORTIFY operates as a shim layer between the controller and the data plane, and dynamically transforms the data plane rules computed by the controller to use Fast Failover groups. FORTIFY can be used off-The-shelf, or customized programmatically to choose specific types of backup paths. Experimental results collected on a production testbed demonstrate that FORTIFY is a practical, high-performance solution to data plane fault tolerance in SDNs. 

Electrochemical‐based memristors are highly attractive that are capable of nonvolatile analog tuning, long‐term state stability, low power consumption, device scalability, and fast switching speeds. Through the combination of film deposition techniques, i.e., vapor phase polymerization and screen printing, fabrication of a poly(4‐(6‐hexyl)‐4H‐dithieno[3,2‐b:2′,3′‐d]pyrrole) (p6DTP)‐based synaptic‐emulating three‐terminal memristor is designed. Through voltage‐driven pulse programming, and square waves with an amplitude of 100 mV and duration of 100 msec, the device exhibits a power consumption of 1 pJmm⁻²per synaptic event. By analyzing the fundamental operational trends of the p6DTP‐based device, simple and advanced integrated applications can be demonstrated along with synaptic‐like responses. This effort is the first presentation of the vapor phase polymerization technique for any dithienopyrrole‐based monomers, along with the physical implementation of any memristive system as an advanced logical circuit, demonstrated here as a cascaded combinational logic gate.